In the monolithic integrated circuit technology, it is usually necessary to isolate various active and/or passive devices from one another in the integrated circuit structure. More recent trends in this technology capitalize on a particular dielectric isolation where a pattern of dielectrically filled trenches, extending from one surface of the integrated circuit to the interior thereof is used to isolate the devices. The method of manufacturing this form of dielectric isolation involves the formation of a pattern (generally in the form of a grid) of deep trenches in a monolithic silicon semiconductor wafer. An insulator liner of silicon dioxide (typically, about 0.15 .mu.m thick) and silicon nitride (typically, about 0.08 .mu.m thick) is then formed on the planar surfaces of the trenches. The oxide liner is used to passivate the any PN junctions that intercept the trench sidewall and the nitride liner serves as a barrier for mobile ions present in insulating layers used in semiconductor chip wiring. An organic material such as polyimide or an inorganic material such as polysilicon or silicon dioxide is then introduced into the trenches to completely fill them. The remaining portions of the monocrystalline silicon wafer are now isolated from one another by the grid of the dielectric material. Semiconductor devices and circuits can now be formed in the isolated monocrystalline silicon regions.
A representative semiconductor device structure comprised of a complementary vertical NPN and lateral PNP (LPNP) transistor formed in the trench isolated silicon region is illustrated in FIGS. 1-3 where FIG. 1 shows the top view and other two figures show cross-sectional views. In FIGS. 1-3, 10 designates the starting P-silicon wafer having an N+ subcollector region 12 and N epitaxial layer 14. A trench 16 having a liner of oxide 18 and nitride 20 and filled completely with a dielectric such as polyimide 21 delineates a central stud or mesa of silicon 22. The epitaxial layer 14 corresponding to the mesa 22, which has been designated by numeral 24, constitutes both the collector of the NPN and base of the LPNP transistors. Likewise, the P doped region 26 serves as both the base of the NPN and collector of the LPNP devices. The N doped and P doped regions 28 and 30 constitute the emitters of the NPN and LPNP transistors, respectively.
Continuing with reference to FIGS. 1-3, the N region 24, which separates the LPNP emitter 30 and NPN base 26 by a narrow (typically about 1.0 .mu.m) width W, is typically doped to a low concentration level of approximately about 10.sup.16 atoms/cc (about two orders of magnitude lower than the concentration level of the P regions 26 and 30) to assure high performance of the complementary device. As a result of this high doping concentration and narrow width W, the localized regions 32 and 34 of the N region 24 adjacent to the sidewalls of the trench 16 are prone to inversion due to the polyimide trench-fill and the trench liner adjacent to the regions 32 and 34 acting as the gate electrode and gate insulator, respectively, of a parasitic field effect transistor (FET). The necessary gate voltage to turn on the parasitic FET is invariably sustained by the polyimide 21. Inversion of regions 32 and 34 leads to charge leakage between the LPNP emitter 30 and collector 26.
Inversion is generally most acute at the upper corner regions 32 and 34 of the silicon mesa 22 because, as indicated in FIGS. 2 and 3, the oxide-nitride liner 18-20 is invariably thinned out at the top corner regions of the trench 16 due to the geometry effects associated with sharp corners. Specifically, the trench liner at the corner regions is reduced by 50% compared to the remainder of the trench surface due to the presence of a silicon nitride layer on the mesa 22 during the trench oxide liner 18 forming step.
Leakage between the highly doped and closely spaced regions P regions 26 and 30 via either of the peripheral edges of the intermediate lightly doped N region 24 also occurs due to inherent presence of charges in the oxide-nitride liner and the polyimide trench fill. To elaborate on this point, the trench liner, particularly the thermal oxide 18 thereof, characteristically contains mobile ions such as those of sodium. Likewise, the polyimide contains negative charges in the form of free hydroxyl ions. The resultant of these various freely moving charges is build up of a sufficiently high amount of charge giving rise to the above leakage.
While the charge leakage problem has been discussed in the context of a complementary bipolar device formed on a trench-defined silicon mesa, it is not so limited. Another situation where this problem plagues semiconductor device fabrication is when the P regions 26 (without the embedded N region 28) and 30 (FIGS. 1-2) are resistor bars. Yet another situation is when the P regions 26 (absent region 28) and 30 are the source and drain, respectively of a FET with the intermediate N region being the FET gate region. In other words, the charge leakage problem occurs whenever a lightly doped narrow region of one conductivity type separates two highly doped regions of an opposite conductivity type so long as the various regions are formed on a trench isolated silicon mesa.
One way of overcoming the above charge leakage problem is to insure that the trench liner is free of any mobile ions and increase the thickness of the liner. However, formation of (oxide) trench liner free of mobile ions is extremely difficult, if not impossible. Certainly, it significantly adds to the cost of fabrication. Also, increasing the thickness of the liner to prevent parasitic FET action means a reduction of the chip area since the oxide is formed by consumption of the silicon, thereby reducing the density of devices on the wafer.
Another alternative is to provide an N+ reach-through diffusion in regions 32 and 34 extending down to the subcollector region 12 to prevent leakage between P regions 26 and 30. However, this solution has a number of disadvantages, First, since each edge of the silicon mesa 22 requires at least 1.5 .mu.m wide real estate for accommodating the reach-through, the mesa 22 should be made at least 3 .mu.m wider. This translates into a reduction in the wafer device density. Specifically in the case of complementary bipolar device fabrication, the above-necessitated increase in the mesa dimensions, in turn, increases the LPNP device size resulting in an increase in the integrated circuit delay due to increased collector-to-base capacitance. Also, formation of reach-through adds second and third order alignment problems to the ground rules which can result in leakage between the NPN emitter and the N+ reach-through channel stop.
Yet another solution to the P-to-P leakage problem is to increase the N dopant concentration level in the epitaxial silicon layer 24. However, by doing so not only the gain of the LPNP transistor is decreased, but also its collector-to-base capacitance will be increased, thereby rendering the LPNP device slow.
Accordingly, it is an object of the present invention to solve these and other problems by means of a straight forward and simple structure.
Specifically, it is an object of the invention to provide a structure which eliminates charge leakage between two closely-spaced, highly and similarly (i.e., both P or N) doped, and trench-defined silicon regions via the trench-defined edges of a lightly (N or P) doped intermediate region therebetween.
It is another object of the invention to provide a structure which does not encroach upon valuable chip real estate.
It is another object of the invention to provide a method of forming the above structure.